Read-only memory (ROM) is a semiconductor memory device containing fixed data patterns determined at fabrication. Because changing a single bit in the stored data would require alteration of the entire circuit and its fabrication, ROMs are often made using a process called mask programming, by which data is typically stored in the ROM at one of the final process steps. The economic advantage of a mask ROM is obvious: all ROMs may be fabricated similarly, and customization takes place only during one of the process steps.
In contrast to conventional ROMs or mask ROMs in which the data must be stored in the device during fabrication, a programmable read-only memory (PROM) allows the user to electrically program the data into the memory. However, a conventional PROM cell can be programmed only once. For example, a typical arrangement employed in a bipolar-junction transistor (BJT) PROM involves the use of polysilicon fuses to connect the emitter the corresponding digit line. Depending on the desired content of the memory cell, the fuses are either left intact or blown open by a large current during programming. Obviously, such a programming step is irreversible.
To improve the conventional non-erasable PROM, several erasable semiconductor memory cells have been developed, including the erasable read-only memory (EPROM), the electrically alterable read-only memory (EAROM), the electrically erasable read-only memory (EEPROM or E.sup.2 PROM), E.sup.2 PROM-EAROM, and the nonvolatile static random-access memory (SRAM). Each of these erasable semiconductor memory cells may be used in a variety of applications. For example, low-density EAROMs (less than 8k) can be used in consumer radio tuners and automotive engine controllers.
A typical way to achieve nonvolatile data storage in the above erasable or alterable programmable memory cells is to use a floating gate, typically located between a control gate and a substrate and capable of holding electrical charges for an indefinite period of time. The control gate and the floating gate are typically made of the same material, e.g., polysilicon, while the substrate generally has a lightly doped source and drain region. When carrying no charges, the floating gate has no influence on the electrical field generated by the control gate in the channel region between the source and the drain. However, if the floating gate is charged with electrons, these electric charges in the floating gate will generate in the channel region an electrical field opposite to the field generated by an active control gate. Thus, if an active signal at the control gate cannot generate a sufficiently strong field to turn on the memory transistor, the transistor will store the value "0." Only with a much higher control gate potential can the memory transistor be turned on and store the value "1". In other words, the field of the control gate must be strong enough to compensate the field of the floating gate and to make the channel between the source and the drain conductive.
To reprogram a conventional EPROM, the electrons in the floating gates are erased by exposure to an ultraviolet (UV) irradiation. Electrons in the floating gates are energized by the UV light and are thus able to leave the floating gates. Nonetheless, to enable the memory chip to be exposed to UV radiation, the package of an EPROM (usually made of ceramics) must have a window made of a material transparent to UV, e.g., quartz glass. In addition, the electric charges in a whole EPROM array are erased all at once, dictating a time-consuming reprogramming process at all the array cells.
Some of the above limitations of the EPROM may be overcome by the use of an E.sup.2 PROM, in which the electric charges in a floating gate can be electrically erased. A cross-sectional view of a typical prior-art stacked-gate E.sup.2 PROM device having two layers of polysilicon is shown in FIG. 1. The substrate 10 is a single-crystal silicon substrate. An active region is defined by an insulating field oxide (FOX) region 12. A first silicon dioxide layer is formed on the substrate 10 as the tunnel oxide layer 14. A first polysilicon layer deposited and lithographically patterned on the tunnel oxide layer 14 to form a floating gate 16. A second silicon dioxide layer is deposited on the floating gate 16 to form an insulating layer 18. Both oxide layers are typically approximately 50 nm thick. A second polysilicon layer is then deposited by a chemical vapor deposition (CVD) process and lithographically patterned on the insulating layer 18 to form a control gate 20. Finally, source 22 and drain 24 regions are formed in the substrate by ion implantation. An n-doped drain 24 and a p-doped substrate 10 thus form a p-n junction in the substrate 10.
An E.sup.2 PROM may be programmed in the same way as an EPROM, e.g., through hot electron injection generated by a voltage pulse between the control gate 20 and the drain 24. In this process, electrons generated in the drain 24 traverse the tunnel oxide layer 14 and accumulate in the floating gate 16. Alternatively, the floating gate 16 may be charged by an avalanche injection mechanism, by which electrical potentials are applied to cause high-energy electrons in the channel region between the source 22 and the drain 24 to be injected across the insulating tunnel oxide layer 14 into the floating gate 16.
To erase the E.sup.2 PROM, an inverse voltage is typically applied between the control gate 20 and the drain 24. As a result, the electrons in the floating gate 16 travel across the tunnel oxide 14 layer into the drain 24; the stored data is thus erased. It is important that this discharge process does not last too long, otherwise too many electrons will tunnel out of the floating gate 16, making it positively charged. Conventional E.sup.2 PROMs have several advantages including byte erase, byte program and random access read capabilities. However, such memory cells generally call for two transistors per bit: a memory transistor and a select transistor, resulting in a relatively large cell size.
Another erasable, nonvolatile memory cell is the flash memory cell, in which the contents of all memory array cells can be erased simultaneously through the use of an electrical erase signal. Flash memories are based on either the EPROM or E.sup.2 PROM technology; the selection between the two requires tradeoffs between the higher density of the EPROM technology and the in-circuit programming flexibility of the E.sup.2 PROM technology. The structure of a flash memory cell is essentially the same as that of an EPROM or E.sup.2 PROM cell, except that the tunnel oxide in a flash memory cell is thinner than that of an E.sup.2 PROM memory cell, thus allowing lower program and erase voltages to be applied between the control gate and the drain. Flash memories have the capability of electrical program, read, and data storage in a memory cell. Although a flash memory does not permit bit-by-bit erasure, it can be electrically programmed and erased in a block-by-block manner.
Although the above prior-art E.sup.2 PROM or flash memory technology have solved a number of problems associated with prior-art EPROMs, several problems still exist during the erasure of stored information in a prior-art E.sup.2 PROM or flash memory cell. First, the typical thickness (approximately 10 nm) of the tunnel oxide layer 14 of EEPROM and flash memory cells does not allow the use of a conventional E.sup.2 PROM power supply to generate an adequate Fowler-Nordheim tunneling current for fast erasure. Second, the use of a higher electrical potential (and hence a higher erasure current) may cause junction breakdown, leading to excessive substrate current during erasure. Third, electrical holes generated by the band-to-band leakage current may be trapped in the tunnel oxide, resulting in the degradation of the tunnel oxide layer.